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1 ? fn8132.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005. all rights reserved all other trademarks mentioned are the property of their respective owners. x5328, x5329 (replaces x25328, x25329) cpu supervisor with 32kbit spi eeprom features ?low v cc detection and reset assertion ?five standard reset threshold voltages ?re-program low v cc reset threshold voltage using special programming sequence ?reset signal valid to v cc = 1v ? long battery life with low power consumption ?<1a max standby current ?<400a max active current during read ? 32kbits of eeprom ? built-in inadvertent write protection ?power-up/power-down protection circuitry ?protect 0, 1/4, 1/2 or all of eeprom array with block lock ? protection ?in circuit programmable rom mode ? 2mhz spi interface modes (0,0 & 1,1) ? minimize eeprom programming time ?32-byte page write mode ?self-timed write cycle ?5ms write cycle time (typical) ? 2.7v to 5.5v and 4.5v to 5.5v power supply operation ? available packages ?14 ld tssop, 8 ld soic, 8 ld pdip ? pb-free plus anneal available (rohs compliant) description these devices combine three popular functions, power- on reset control, supply voltage supervision, and block lock protect serial eeprom memory in one package. this combination lowers system cost, reduces board space requirements, and increases reliability. applying power to the device activates the power-on reset circuit which holds reset /reset active for a period of time. this allows the power supply and oscilla- tor to stabilize before the processor can execute code. the device?s low v cc detection circuitry protects the user?s system from low volt age conditions by holding reset /reset active when v cc falls below a mini- mum v cc trip point. reset /reset remains asserted until v cc returns to proper operating level and stabi- lizes. five industry standard v trip thresholds are available, however, intersil?s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold in applica- tions requiring higher precision. block diagram data register command decode & control logic si so sck cs v cc reset timebase power-on and generation v trip + - reset /reset reset low voltage status register protect logic 8kbits 8kbits 16kbits eeprom array wp x5328 = reset x5329 = reset data sheet october 17, 2005
2 fn8132.1 october 17, 2005 ordering information part number reset (active low) part marking part number reset (active high) part marking v cc range (v) v trip range temp range (c) package x5328p-4.5a x5329p-4.5a 4.5-5.5 4.5-4.75 0 to 70 8 ld pdip x5328pz-4.5a (note) x5328p z al x5329pz-4.5a (note) x5329p z al 0 to 70 8 ld pdip (pb-free) x5328pi-4.5a x5329pi-4.5a -40 to 85 8 ld pdip x5328piz-4.5a (note) x5328p z am x5329piz-4.5a (note) x5329p z am -40 to 85 8 ld pdip (pb-free) x5328s8-4.5a x5328 al x5329s8-4.5a 0 to 70 8 ld soic x5328s8z-4.5a (note) x5328 z al x5329s8z-4.5a (note) x5329 z al 0 to 70 8 ld soic (pb-free) x5328s8i-4.5a x5328 am x5329s8i-4.5a -40 to 85 8 ld soic x5328s8iz-4.5a (note) x5328 z am x5329s8iz-4.5a (note) x5329 z am -40 to 85 8 ld soic (pb-free) x5328v14-4.5a x5329v14-4.5a 0 to 70 14 ld tssop x5328v14z-4.5a (note) x5328v z al x5329v14z-4.5a (note) x5329v z al 0 to 70 14 ld tssop (pb-free) x5328v14i-4.5a x5329v14i-4.5a -40 to 85 14 ld tssop x5328v14iz-4.5a (note) x5328v z am x5329v14iz-4.5a (note) x5329v z am -40 to 85 14 ld tssop (pb-free) x5328p x5328p x5329p x5329p 4.5-5.5 4.25-4.5 0 to 70 8 ld pdip x5328pz (note) x5328p z x5329pz (note) x5329p z 0 to 70 8 ld pdip (pb-free) x5328pi x5328p i x5329pi x5329p i -40 to 85 8 ld pdip x5328piz (note) x5328p z i x5329piz (note) x5329p z i -40 to 85 8 ld pdip (pb-free) x5328s8* x5328 x5329s8* 0 to 70 8 ld soic x5328s8z* (note) x5328 z x5329s8z* (note) x5329 z 0 to 70 8 ld soic (pb-free) x5328s8i* x5328 i x5329s8i* -40 to 85 8 ld soic x5328s8iz* (note) x5328 z i x5329s8iz* (note) x5329 z i -40 to 85 8 ld soic (pb-free) x5328v14* x5328v x5329v14* 0 to 70 14 ld tssop x5328v14z* (note) x5328v z x5329v14z* (note) x5329v z 0 to 70 14 ld tssop (pb-free) x5328v14i* x5329v14i* -40 to 85 14 ld tssop x5328v14iz* (note) x5328v z i x5329v14iz* (note) x5329v z i -40 to 85 14 ld tssop (pb-free) x5328p-2.7a x5329p-2.7a 2.7-5.5 2.85-3.0 0 to 70 8 ld pdip x5328pz-2.7a (note) x5328p z an x5329pz-2.7a (note) x5329p z an 0 to 70 8 ld pdip (pb-free) x5328pi-2.7a x5329pi-2.7a -40 to 85 8 ld pdip x5328piz-2.7a (note) x5328p z ap x5329piz-2.7a (note) x5329p z ap -40 to 85 8 ld pdip (pb-free) x5328s8-2.7a x5328 an x5329s8-2.7a 0 to 70 8 ld soic x5328s8z-2.7a (note) x5328 z an x5329s8z-2.7a (note) x5329 z an 0 to 70 8 ld soic (pb-free) x5328s8i-2.7a x5328 ap x5329s8i-2.7a -40 to 85 8 ld soic x5328s8iz-2.7a (note) x5328 z ap x5329s8iz-2.7a (note) x5329 z ap -40 to 85 8 ld soic (pb-free) x5328v14-2.7a x5328v an x5329v14-2.7a 0 to 70 14 ld tssop x5328v14z-2.7a (note) x5328v z an x5329v14z-2.7a (note) x5329v z an 0 to 70 14 ld tssop (pb-free) x5328, x5329
3 fn8132.1 october 17, 2005 x5328v14i-2.7a x5329v14i-2.7a 2.7-5.5 2.85-3.0 -40 to 85 14 ld tssop x5328v14iz-2.7a (note) x5328v z ap x5329v14iz-2.7a (note) x5329v z ap -40 to 85 14 ld tssop (pb-free) x5328p-2.7 x5328p f x5329p-2.7 x5329p f 2.7-5.5 2.55-2.7 0 to 70 8 ld pdip x5328pz-2.7 (note) x5328p z f x5329pz-2.7 (note) x5329p z f 0 to 70 8 ld pdip (pb-free) x5328pi-2.7 x5328p g x5329pi-2.7 x5329p g -40 to 85 8 ld pdip x5328piz-2.7 (note) x5328p z g x5329piz-2.7 (note) x5329p z g -40 to 85 8 ld pdip (pb-free) x5328s8-2.7* x5328 f x5329s8-2.7* 0 to 70 8 ld soic x5328s8z-2.7* (note) x5328 z f x5329s8z-2.7* (note) x5329 z f 0 to 70 8 ld soic (pb-free) x5328s8i-2.7* x5328 g x5329s8i-2.7* -40 to 85 8 ld soic x5328s8iz-2.7* (note) x5328 z g x5329s8iz-2.7* (note) x5329 z g -40 to 85 8 ld soic (pb-free) x5328v14-2.7* x5329v14-2.7* 0 to 70 14 ld tssop x5328v14z-2.7* (note) x5328v z f x5329v14z-2.7* (note) x5329v z f 0 to 70 14 ld tssop (pb-free) x5328v14i-2.7* x5329v14i-2.7* -40 to 85 14 ld tssop x5328v14iz-2.7* (note) x5328v z g x5329v14iz-2.7* (note) x5329v z g -40 to 85 14 ld tssop (pb-free) *add "t1" suffix for tape and reel. note: intersil pb-free plus anneal products employ special pb-free material sets ; molding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free sol dering operations. intersil pb- free products are msl classified at pb-free peak reflow tem peratures that meet or exceed the pb-free requirements of ipc/jedec j std-020. ordering information (continued) part number reset (active low) part marking part number reset (active high) part marking v cc range (v) v trip range temp range (c) package x5328, x5329
4 fn8132.1 october 17, 2005 pin description pin configuration pin (soic/pdip) pin tssop name function 11cs chip select input. cs high, deselects the device and the so output pin is at a high impedance state. unless a nonvolatile write cycle is underway, the device will be in the standby power mode. cs low enables the device, placing it in the active power mode. prior to the start of any operation after power-up, a high to low transition on cs is required. 22so serial output. so is a push/pull serial data output pin. a read cycle shifts data out on this pin. the falling edge of the serial clock (sck) clocks the data out. 58si serial input. si is a serial data input pin. input all opcodes, byte addresses, and memory data on this pin. the rising edge of the serial clock (sck) latches the input data. send all opcodes (table 1), addresses and data msb first. 69sck serial clock. the serial clock controls the serial bus timing for data input and out- put. the rising edge of sck latches in the opcode, address, or data bits present on the si pin. the falling edge of sck changes the data output on the so pin. 36wp write protect. the wp pin works in conjunction with a nonvolatile wpen bit to ?lock? the setting of the watchdog timer control and the memory write protect bits. 47v ss ground 814v cc supply voltage 7 13 reset / reset reset output . reset /reset is an active low/high, open drain output which goes active whenever v cc falls below the minimum v cc sense level. it will remain active until v cc rises above the minimum v cc sense level for 200ms. reset /reset goes active on power-up at about 1v and remains active for 200ms after the power supply stabilizes. 3-5,10-12 nc no internal connections 8 ld soic/pdip cs wp so 1 2 3 4 reset /reset 8 7 6 5 14 ld tssop so wp v ss 1 2 3 4 5 6 7 reset /reset sck si 14 13 12 11 10 9 8 nc v cc nc x5328/29 v cc sck si cs nc nc nc nc x5328/29 v cc x5328, x5329
5 fn8132.1 october 17, 2005 principles of operation power-on reset application of power to the x5328/x5329 activates a power-on reset circuit. this circuit goes active at about 1v and pulls the reset /reset pin active. this signal prevents the system microprocessor from start- ing to operate with insufficient voltage or prior to stabi- lization of the oscillator. when v cc exceeds the device v trip value for 200ms (nominal) the circuit releases reset /reset, allowing the proc essor to begin exe- cuting code. low voltage monitoring during operation, the x5328/x5329 monitors the v cc level and asserts reset /reset if supply voltage falls below a preset minimum v trip . the reset /reset signal prevents the microprocessor from operating in a power fail or brownout condition. the reset /reset signal remain s active until the voltage drops below 1v. it also remains active until v cc returns and exceeds v trip for 200ms. v cc threshold reset procedure the x5328/x5329 has a standard v cc threshold (v trip ) voltage. this value will not change over normal operating and storage conditions. however, in applica- tions where the standard v trip is not exactly right, or for higher precision in the v trip value, the x5328/x5329 threshold may be adjusted. setting the v trip voltage this procedure sets the v trip to a higher voltage value. for example, if the current v trip is 4.4v and the new v trip is 4.6v, this procedure directly makes the change. if the new settin g is lower than the current setting, then it is necessar y to reset the trip point before setting the new value. to set the new v trip voltage, apply the desired v trip threshold to the v cc pin and tie the cs pin and the wp pin high. reset /reset and so pins are left uncon- nected. then apply the programming voltage v p to both sck and si and pulse cs low then high. remove v p and the sequence is complete. figure 1. set v trip voltage resetting the v trip voltage this procedure sets the v trip to a ?native? voltage level. for example, if the current v trip is 4.4v and the v trip is reset, the new v trip is something less than 1.7v. this procedure must be used to set the voltage to a lower value. to reset the v trip voltage, apply a voltage between 2.7 and 5.5v to the v cc pin. tie the cs pin, the wp pin, and the sck pin high. reset /reset and so pins are left unconnected. then apply the program- ming voltage v p to the si pin only and pulse cs low then high. remove v p and the sequence is complete. figure 2. reset v trip voltage sck si v p v p cs sck si v cc v p cs x5328, x5329
6 fn8132.1 october 17, 2005 figure 3. v trip programming sequence flow chart figure 4. sample v trip reset circuit v trip programming apply 5v to v cc decrement v cc reset pin goes active? measured v trip - desired v trip done execute sequence reset v trip set v cc = v cc applied = desired v trip execute sequence set v trip new v cc applied = old v cc applied + error (v cc = v cc - 10mv) execute sequence reset v trip new v cc applied = old v cc applied - error error emax error < emax yes no error > emax emax = maximum desired error 1 2 3 4 8 7 6 5 x5328/29 v trip adj. program nc nc v p reset v trip test v trip set v trip nc reset 4.7k 4.7k 10k 10k + x5328, x5329
7 fn8132.1 october 17, 2005 spi serial memory the memory portion of the device is a cmos serial eeprom array with intersil?s block lock protection. the array is internally organized as x 8. the device features a serial peripheral interface (spi) and software protocol allowing operation on a simple four-wire bus. the device utilizes intersil?s proprietary direct write ? cell, providing a minimu m endurance of 100,000 cycles and a minimum data retention of 100 years. the device is designed to interface directly with the synchronous serial peripheral interface (spi) of many popular microcontroller familie s. it contains an 8-bit instruction register that is accessed via the si input, with data being clocked in on the rising edge of sck. cs must be low during the entire operation. all instructions (table 1), addresses and data are transferred msb first. data input on the si line is latched on the first rising edge of sck after cs goes low. data is outp ut on the so line by the falling edge of sck. sck is static, allowing the user to stop the clock and then start it ag ain to resume operations where left off. write enable latch the device contains a write enable latch. this latch must be set before a write operation is initiated. the wren instruction will set the latch and the wrdi instruction will reset the latc h (figure 3). this latch is automatically reset upon a power-up condition and after the completion of a valid write cycle. status register the rdsr instruction provides access to the status register. the status regist er may be read at any time, even during a write c ycle. the status register is formatted as follows: *bits (5,4) should be written as ?1? only. the write-in-progress (wip) bi t is a volatile, read only bit and indicates whether the device is busy with an internal nonvolatile write operation. the wip bit is read using the rdsr instruction. when set to a ?1?, a non- volatile write operation is in progress. when set to a ?0?, no write is in progress. table 1. instruction set note: *instructions are shown msb in leftmost pos ition. instructions are transferred msb first. table 2. block protect matrix 7 65432 1 0 wpen flb 1* 1* bl1 bl0 wel wip instruction name instru ction format* operation wren 0000 0110 set the write enable latch (enable write operations) sflb 0000 0000 set flag bit wrdi/rflb 0000 0100 reset the write enable latch/reset flag bit rsdr 0000 0101 read status register wrsr 0000 0001 write status register (block lock, wpen & flag bits) read 0000 0011 read data from memory array beginning at selected address write 0000 0010 write data to memory array beginning at selected address wren cmd status register device pin block block status register wel wpen wp# protected block unprotected block wpen, bl0, bl1, wd0, wd1 0 x x protected protected protected 1 1 0 protected writable protected 1 0 x protected writable writable 1 x 1 protected writable writable x5328, x5329
8 fn8132.1 october 17, 2005 the write enable latch (wel) bit indicates the status of the write enable latch. when wel = 1, the latch is set high and when wel = 0 the latch is reset low. the wel bit is a volatile, read only bit. it can be set by the wren instruction and can be reset by the wrds instruction. the block lock bits, bl0 and bl1, set the level of block lock protection. these nonvolatile bits are pro- grammed using the wrsr instruction and allow the user to protect one quarter, one half, all or none of the eeprom array. any portion of the array that is block lock protected can be read but not written. it will remain protected until the bl bits are altered to disable block lock protection of that portion of memory. the flag bit shows the status of a volatile latch that can be set and reset by the system using the sflb and rflb instructions. the flag bit is automatically reset upon power-up. the nonvolatile wpen bit is programmed using the wrsr instruction. this bit works in conjunction with the wp pin to provide an in-circuit programmable rom function (table 2). wp is low and wpen bit pro- grammed high disables al l status register write operations. in circuit programmable rom mode this mechanism protects the block lock and watchdog bits from inadvertent corruption. in the locked state ( programmable rom mode) the wp pin is low and the nonvolatil e bit wpen is ?1?. this mode disables nonvolatile writ es to the device?s status register. setting the wp pin low while wpen is a ?1? while an internal write cycle to the status register is in progress will not stop this write oper ation, but the operation dis- ables subsequent write attempts to the status register. when wp is high, all functions, including nonvolatile writes to the status register operate normally. setting the wpen bit in the status register to ?0? blocks the wp pin function, allowing writes to the status register when wp is high or low. setting the wpen bit to ?1? while the wp pin is low activates the pro- grammable rom mode, thus requiring a change in the wp pin prior to subsequent status register changes. this allows manufacturing to install the device in a sys- tem with wp pin grounded and still be able to program the status register. manuf acturing can then load con- figuration data, manufacturing time and other parame- ters into the eeprom, t hen set the portion of memory to be protected by setting t he block lock bits, and finally set the ?otp mode? by se tting the wpen bit. data changes now require a hardware change. figure 5. read eepr om array sequence status register bits array addresses protected bl1 bl0 x5328/x5329 0 0 none 0 1 $0c00-$0fff 1 0 $0800-$0fff 1 1 $0000-$0fff 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 7 654321 0 data out cs sck si so msb high impedance instruction 16 bit address 15 14 13 3 2 1 0 x5328, x5329
9 fn8132.1 october 17, 2005 read sequence when reading from the eeprom memory array, cs is first pulled low to select the device. the 8-bit read instruction is transmitted to the device, followed by the 16-bit address. after the read opcode and address are sent, the data stored in the memory at the selected address is shifted out on the so line. the data stored in memory at the next address can be read sequen- tially by continuing to provide clock pulses. the address is automatically incremented to the next higher address after each byte of data is shifted out. when the highest address is reached, the address counter rolls over to address $0000 allowing the read cycle to be continued indefinitely. the read operation is terminated by taking cs high. refer to the read eeprom array sequence (figure 1). to read the status register, the cs line is first pulled low to select the device followed by the 8-bit rdsr instruction. after the rdsr opcode is sent, the contents of the status register are shifted out on the so line. refer to the read status r egister sequence (figure 2). write sequence prior to any attempt to writ e data into th e device, the ?write enable? latch (wel) must first be set by issu- ing the wren instru ction (figure 3). cs is first taken low, then the wren instruction is clocked into the device. after all eight bits of the instruction are trans- mitted, cs must then be taken high. if the user con- tinues the write operation without taking cs high after issuing the wren instruction, the write opera- tion will be ignored. to write data to the eeprom memory array, the user then issues the write in struction followed by the 16-bit address and then the data to be written. any unused address bits are specified to be ?0?s?. the write operation minimally takes 32 clocks. cs must go low and remain low for the duration of the opera- tion. if the address counter reaches the end of a page and the clock continues, the counter will roll back to the first address of the page and overwrite any data that may have been previously written. for the page write operation (byte or page write) to be completed, cs can only be brought high after bit 0 of the last data byte to be written is clocked in. if it is brought high at any other time, the write operation will not be completed (figure 4). to write to the status regi ster, the wrsr instruction is followed by the data to be written (figure 5). data bits 0 and 1 must be ?0?. while the write is in progres s following a status regis- ter or eeprom sequence, th e status register may be read to check the wip bit. during this time the wip bit will be high. operational notes the device powers-up in the following state: ? the device is in the low power standby state. ? a high to low transition on cs is required to enter an active state and re ceive an instruction. ? so pin is high impedance. ? the write enable latch is reset. ? the flag bit is reset. ? reset signal is active for t purst . data protection the following circuitry has been included to prevent inadverten t writes: ? a wren instruction must be issued to set the write enable latch. ?cs must come high at th e proper clock count in order to start a nonvolatile write cycle. x5328, x5329
10 fn8132.1 october 17, 2005 figure 6. read status register sequence figure 7. write enable latch sequence figure 8. write sequence 01234567891011121314 76543210 cs sck si so msb high impedance instruction data out 01234567 cs si sck high impedance so 32 33 34 35 36 37 38 39 sck si cs 012345678910 sck si instruction 16 bit address data byte 1 76543210 cs 40 41 42 43 44 45 46 47 data byte 2 76543210 data byte 3 76543210 15 14 13 3 2 1 0 20 21 22 23 24 25 26 27 28 29 30 31 65 4 321 0 data byte n x5328, x5329
11 fn8132.1 october 17, 2005 figure 9. status register write sequence symbol table 0123456789 cs sck si so high impedance instruction data byte 765432 10 10 11 12 13 14 15 waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance x5328, x5329
12 fn8132.1 october 17, 2005 absolute maximum ratings temperature under bias .................... -65c to +135c storage temperature ............ ............ -65c to +150c voltage on any pin with respect to v ss ...................................... -1.0v to +7v d.c. output current ............................................... 5ma lead temperature (soldering, 10s) .................... 300c comment stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device (at these or any ot her conditions above those listed in the operational sections of this specification) is not implied. exposure to absolute maximum rating con- ditions for extended periods ma y affect device reliability. d.c. operating characteristics (over the recommended operating condit ions unless otherwise specified.) capacitance t a = +25c, f = 1mhz, v cc = 5v notes: (1) v il min. and v ih max. are for reference only and are not tested. (2) this parameter is periodically sampled and not 100% tested. symbol parameter limits unit test conditions min. typ. max. i cc1 v cc write current (active) 5 ma sck = v cc x 0.1/v cc x 0.9 @ 2mhz, so = open i cc2 v cc read current (active) 0.4 ma sck = v cc x 0.1/v cc x 0.9 @ 2mhz, so = open i sb v cc standby current 1 a cs = v cc , v in = v ss or v cc , v cc = 5.5v i li input leakage current 0.1 10 a v in = v ss to v cc i lo output leakage current 0.1 10 a v out = v ss to v cc v il (1) input low voltage -0.5 v cc x 0.3 v v ih (1) input high voltage v cc x 0.7 v cc + 0.5 v v ol1 output low voltage 0.4 v v cc > 3.3v, i ol = 2.1ma v ol2 output low voltage 0.4 v 2v < v cc 3.3v, i ol = 1ma v ol3 output low voltage 0.4 v v cc 2v, i ol = 0.5ma v oh1 output high voltage v cc - 0.8 v v cc > 3.3v, i oh = -1.0ma v oh2 output high voltage v cc - 0.4 v 2v < v cc 3.3v, i oh = -0.4ma v oh3 output high voltage v cc - 0.2 v v cc 2v, i oh = -0.25ma v ols reset output low voltage 0.4 v i ol = 1ma symbol test max. unit conditions c out (2) output capacitance (so, reset , reset) 8 pf v out = 0v c in (2) input capacitance (sck, si, cs , wp )6pfv in = 0v recommended operating conditions temperature min. max. commercial 0c 70c industrial -40c +85c voltage option supply voltage -2.7 or -2.7a 2.7v to 5.5v blank or -4.5a 4.5v-5.5v x5328, x5329
13 fn8132.1 october 17, 2005 equivalent a.c. load circuit at 5v v cc a.c. test conditions a.c. characteristics (over recommended operating condit ions, unless otherwise specified) serial input timing 5v output 100pf 5v 4.6k ? reset /reset 30pf 2.06k ? 3.03k ? input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x0.5 symbol parameter 2.7-5.5v unit min. max. f sck clock frequency 0 2 mhz t cyc cycle time 500 ns t lead cs lead time 250 ns t lag cs lag time 250 ns t wh clock high time 200 ns t wl clock low time 250 ns t su data setup time 50 ns t h data hold time 50 ns t ri (3) input rise time 100 ns t fi (3) input fall time 100 ns t cs cs deselect time 500 ns t wc (4) write cycle time 10 ms x5328, x5329
14 fn8132.1 october 17, 2005 serial input timing serial output timing notes: (3) this parameter is periodically sampled and not 100% tested. (4) t wc is the time from the rising edge of cs after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle. serial output timing sck cs si so msb in t su t ri t lag t lead t h lsb in t cs t fi high impedance symbol parameter 2.7-5.5v unit min. max. f sck clock frequency 0 2 mhz t dis output disable time 250 ns t v output valid from clock low 250 ns t ho output hold time 0 ns t ro (3) output rise time 100 ns t fo (3) output fall time 100 ns sck cs so si msb out msb?1 out lsb out addr lsb in t cyc t v t ho t wl t wh t dis t lag x5328, x5329
15 fn8132.1 october 17, 2005 power-up and po wer-down timing reset output timing note: (5) this parameter is periodically sampled and not 100% tested. symbol parameter min. typ. max. unit v trip reset trip point voltage, x5328-4.5a, x5328-4.5a reset trip point voltage, x5328, x5329 reset trip point voltage, x5328-2.7a, x5329-2.7a reset trip point voltage, x5328-2.7, x5329-2.7 4.5 4.25 2.85 2.55 4.63 4.38 2.93 2.63 4.75 4.5 3.0 2.7 v v th v trip hysteresis (high to low vs. low to high v trip voltage) 20 mv t purst power-up reset time out 100 200 280 ms t rpd (5) v cc detect to reset/output 500 ns t f (5) v cc fall time 100 s t r (5) v cc rise time 100 s v rvalid reset valid v cc 1v v cc t purst t r t f t rpd reset (x5328) 0 volts v trip reset (x5329) v trip t purst x5328, x5329
16 fn8132.1 october 17, 2005 v trip set conditions v trip reset conditions sck si v p v p cs t vps t vph t p t vps t vph t rp t vpo t vpo t tsu t thd v trip v cc sck si v cc v p cs t vps t vph t p t vps t vp1 t rp t vpo t vpo v cc * *v cc > programmed v trip x5328, x5329
17 fn8132.1 october 17, 2005 v trip programming specifications v cc = 1.7-5.5v; temperature = 0c to 70c parameter description min. max. unit t vps sck v trip program voltage setup time 1 s t vph sck v trip program voltage hold time 1 s t p v trip program pulse width 1 s t tsu v trip level setup time 10 s t thd v trip level hold (stable) time 10 ms t wc v trip write cycle time 10 ms t rp v trip program cycle recovery period (betw een successive programming cycles) 10 ms t vpo sck v trip program voltage off time before next cycle 0 ms v p programming voltage 15 18 v v tran v trip programed voltage range 1.7 5.0 v v ta1 initial v trip program voltage accuracy (v cc applied-v trip ) (programmed at 25c.) -0.1 +0.4 v v ta2 subsequent v trip program voltage accuracy [(v cc applied-v ta1 )-v trip ] (programmed at 25c.) -25 +25 mv v tr v trip program voltage repeatability (successive program operations.) (programmed at 25c) -25 +25 mv v tv v trip program variation after programming (0-75c). (programmed at 25c) -25 +25 mv v trip programming parameters are periodically sampled and are not 100% tested. x5328, x5329
18 fn8132.1 october 17, 2005 typical performance v cc supply current vs. temperature (i sb ) v trip vs. temperature (programmed at 25c) t purst vs. temperature 5.025 5.000 4.975 3.525 3.500 3.475 2.525 2.500 2.475 025 85 voltage temperature v trip = 5v v trip = 3.5v v trip = 2.5v 200 195 190 185 180 175 170 165 160 -40 25 90 degrees c 205 time (ms) 2 1 0 (v cc = 3v, 5v) -40c 25c 90c tempc isb (a) x5328, x5329
19 fn8132.1 october 17, 2005 packaging information note: 1. all dimensions in inches (i n parentheses in millimeters) 2. package dimensions exclude molding flash 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) ref. pin 1 index 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) pin 1 seating 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) typ. 0.010 (0.25) 0 15 8-lead plastic dual in-line package type p half shoulder width on all end pins optional .073 (1.84) max. 0.325 (8.25) 0.300 (7.62) plane x5328, x5329
20 fn8132.1 october 17, 2005 packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 - 8 x 45 8-lead plastic small outline gull wing package type s note: all dimensions in inches (in parentheses in millimeters) 0.250" 0.050" typical 0.050" typical 0.030" typical 8 places footprint x5328, x5329
21 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8132.1 october 17, 2005 packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.020 (0.51) pin 1 pin 1 index 0.050 (1.27) 0.336 (8.55) 0.345 (8.75) 0.004 (0.10) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 14-lead plastic small outlin e gullwing package type s note: all dimensions in inches (in parentheses in millimeters) 0.250" 0.050"typical 0.050"typical 0.030"typical 14 places footprint 0.010 (0.25) 0.020 (0.50) 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 - 8 x 45 x5328, x5329

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